A SMART DESIGN METHODOLOGY WITH DISTRIBUTED EXTRA GATE-ARRAYS FOR ADVANCED ULSI MEMORIES

Authors
TSUKUDE M ARIMOTO K ASAKURA M HIDAKA H FUJISHIMA K
Citation
M. Tsukude et al., A SMART DESIGN METHODOLOGY WITH DISTRIBUTED EXTRA GATE-ARRAYS FOR ADVANCED ULSI MEMORIES, IEICE transactions on electronics, E76C(11), 1993, pp. 1589-1594
Citations number
NO
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEICE transactions on electronics → ACNP
ISSN journal
09168524
Volume
E76C
Issue
11
Year of publication
1993
Pages
1589 - 1594
Database
ISI
SICI code
0916-8524(1993)E76C:11<1589:ASDMWD>2.0.ZU;2-8
Abstract
We propose a smart design methodology for advanced ULSI memories to re duce the turn around time(TAT) for circuit revisions with no area pena lty. This methodology was executed by distributing extra gate-arrays, which were composed of the n-channel and p-channel transistors, under the power line and the signal line. This method was applied to the dev elopment of a 16 Mb DRAM with double metal wiring. The design TAT can be reduced to 1/8 using 1500 gates. This design methodology has been c onfirmed to be very effective.