A LINE-MODE TEST WITH DATA REGISTER FOR ULSI MEMORY ARCHITECTURE

We propose an advanced hyper parallel testing method which improves th e line-mode test method by adding data inversion registers which we ca ll the Advanced Line-mode Test (ALT). This testing method has the same testing capability as the conventional bit-by-bit and multi-bit test method (MBT), because it enables the application of a high sensitive a nd practical test patterns under the hyper parallel condition. The tes ting time for fixed data patterns are reduced by 1/1900 (all-0/1, chec ker board, and etc.). Moreover, the ALT can be applicable to the conti nuous patterns (march, walking, and etc.). The ALT improved from the l ine-mode test with registers and comparators (LTR) is able to applicab le to the most test patterns and to reduce the testing time remarkably , and is suitable for the ULSI memories.