NOISE-REDUCTION TECHNIQUES FOR A 64-KB ECL-CMOS SRAM WITH A 2-NS CYCLE TIME

An ECL-CMOS SRAM technology is proposed which features a combination o f ECL word drivers, ECL write circuits and low-voltage CMOS cells. Thi s technology assures both ultra-high-speed and high-density. In the EC L-CMOS SRAM, various kinds of noise generated during the write cycle s eriously affect the memory performance, because it has much faster acc ess than conventional SRAMs. To overcome this problem, we propose thre e noise reduction techniques; a noise reduction clamp circuit, an emit ter follower with damping capacitor and a twisted bit line structure w ith ''normally on'' equalizer. These techniques allow fast access and cycle times. To evaluate these techniques, a 64-kb SRAM chip was fabri cated using 0.5-mum BiCMOS technology. This SRAM has a short cycle tim e of 2 ns and a very fast access time of 1.5 ns. Evaluation proves the usefulness of these techniques.