STATISTICAL MEMORY YIELD ANALYSIS AND REDUNDANCY DESIGN CONSIDERING FABRICATION LINE IMPROVEMENT

Authors
IMAMIYA K MIYAMOTO J OHTSUKA N TOMITA N IYAMA Y
Citation
K. Imamiya et al., STATISTICAL MEMORY YIELD ANALYSIS AND REDUNDANCY DESIGN CONSIDERING FABRICATION LINE IMPROVEMENT, IEICE transactions on electronics, E76C(11), 1993, pp. 1626-1631
Citations number
NO
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEICE transactions on electronics → ACNP
ISSN journal
09168524
Volume
E76C
Issue
11
Year of publication
1993
Pages
1626 - 1631
Database
ISI
SICI code
0916-8524(1993)E76C:11<1626:SMYAAR>2.0.ZU;2-N
Abstract
The method to optimize redundancy scheme for memory devices is propose d. Yield for new generation memories is predicted by failure mode anal ysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this y ield prediction. The actual data of 16 Mbit EPROM failure analysis ind icate the effectiveness of the prediction.