A BITLINE CONTROL-CIRCUIT SCHEME AND REDUNDANCY TECHNIQUE FOR HIGH-DENSITY DYNAMIC CONTENT-ADDRESSABLE MEMORIES

This paper describes a bitline control circuit and redundancy techniqu e for high-density dynamic content addressable memories (CAMs). The pr oposed bitline control circuit can efficiently manage a dynamic CAM ce ll accompanied by complex operations; that is, a refresh operation, a masked search operation, and partial writing, in addition to normal re ad/write/search operations. By adding a small supplementary circuit to the bitline control circuit, a circuit scheme with redundancy which p revents disabled column circuits from affecting a match operation can also be obtained. These circuit technologies achieve higher-density dy namic CAMs than conventional static CAMs. These technologies have been successfully applied to a 288-kbit CAM with a typical cycle time of 1 50 ns.