A REDUCED-AREA SCHEME FOR CARRY-SELECT ADDERS

The carry-select or conditional-sum adders require carry-chain evaluat ions for each block for both the values of block-carry-in, 0 and 1. Th is paper introduces a scheme to generate carry bits with block-carry-i n 1 from the carries of a block with block-carry-in 0. This scheme is then applied to carry-select and parallel-prefix adders to derive a mo re area-efficient implementation for both the cases. The proposed carr y-select scheme is assessed relative to carry-ripple, classical carry- select, and carry-skip adders. The analytic evaluation is done with re spect to the gate-count model for area and gate-delay units for time. The gate-count of the proposed carry-select scheme is 25% higher than that of a carry-skip adder for a 30% gain in speed. The proposed varia tion of parallel-prefix adder, select-prefix adder, takes 5n + log2 n/ 2 fewer gates than an n-bit parallel-prefix adder. It is also faster b y 1 gate delay. The select-prefix adder when built with parallel-prefi x blocks of equal size gives rise to a family of select-prefix adders that cover the area-time performance gap between a carry-select/carry- skip adder and a full carry-look-ahead adder. The CMOS implementations of these two adder designs corroborate the analytical results. The pr oposed carry-select adder is about 24.3% faster than a carry-skip adde r with equal-sized blocks, but takes 7% additional area. The select-pr efix adder has a 20% area advantage over a parallel-prefix adder with a simultaneous time advantage of the order of 23%.