TRANSPARENT RANDOM-ACCESS MEMORY TESTING FOR PATTERN SENSITIVE FAULTS

This paper presents a new methodology for RAM testing based on the PS( n, k) fault model (the k out of n pattern sensitive fault model). Acco rding to this model the contents of any memory cell which belongs to a n n-bit memory block, or the ability to change the contents, is influe nced by the contents of any k-1 cells from this block. The proposed me thodology is a transparent BIST technique, which can be efficiently co mbined with on-line error detection. This approach preserves the initi al contents of the memory after the rest and provides for a high fault coverage for traditional fault and error models, as well as for patte rn sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its appro ximations by deterministic and pseudorandom circular tests. The propos ed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches .