MODULAR IMPLEMENTATION OF EFFICIENT SELF-CHECKING CHECKERS FOR THE BERGER CODE

A technique for designing efficient checkers for conventional Berger c ode is proposed in this paper. The check bits are derived by partition ing the information bits into two blocks, and then using an addition a rray to sum the number of 1's in each block. The check bit generator c ircuit uses a specially designed 4-input 1's counter. Two other types of 1's counters having 2 and 3 inputs are also used to realize checker s for variable length information bits. Several variations of 2-bit ad der circuits are used to add the number of 1's. The check bit generato r circuit uses gates with fan-in of less than or equal to 4 to simplif y implementation in CMOS. The technique achieves significant improveme nt in gate count as well as speed over existing approaches.