A 1.71-MILLION TRANSISTOR CMOS CPU CHIP WITH A TESTABLE CACHE ARCHITECTURE

A 1.71-million transistor CISC CPU chip for the business computer has been developed. The chip is implemented in a 0.8-mu m CMOS double-poly silicon double-metal technology. The 16.3-mm x 12.7-mm device contains a 16-kilobyte cache and 192 entries TLB and operates at 40 MHz. The s ustained high performance in a complexed instruction set has been real ized by a large horizontal microprogram that controls two 32-b ALU's. The cache and TLB employ a 77-mu m(2) SRAM using load resistors formed by the second polysilicon; these are accessed in one-half clock cycle and are tested at an 8 bytes per clock rate utilizing a new test stra tegy.