A 30-NS 256-MB DRAM WITH A MULTIDIVIDED ARRAY STRUCTURE

A 256-Mb DRAM with a multidivided array structure has been developed a nd fabricated with 0.25-mu m CMOS technology. It features 30-ns access time, 16-b I/O's, and a 35-mA operating current at a 60-ns cycle time . Three key circuit technologies were used in its design: a partial ce ll array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to incre ase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing o perational margin. Memory cell size was 0.72 mu m(2). Use of the trenc h isolated cell transistor and the HSG cylindrical stacked capacitor c ells helped reduce chip size to 333 mm(2).