256-MB DRAM CIRCUIT TECHNOLOGIES FOR FILE APPLICATIONS

256-Mb DRAM circuit technologies characterized by low power and high f abrication yield for file applications are described. The newly propos ed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the subthreshold current to 3% of the conventional scheme, and a subarray-replacement redundancy technique that doubles chip yield and consequently reduces manufacturing costs. An experimental 256-Mb DRAM has been designed and fabricated by combin ing the proposed circuit techniques and a 0.25-mu m phase-shift optica l lithography, and its basic operations are verified. A 0.72-mu m(2) d ouble-cylindrical recessed stacked-capacitor (RSTC) cell is used to en sure a storage capacitance of 25 fF/cell. A typical access time under a 2-V power supply voltage was 70 ns. With the proper device character istics, the simulated performances of the 256-Mb DRAM operating with a 1.5-V power supply voltage are a data-retention current of 53 mu A an d an access time of 48 ns.