A SINGLE-BIT-LINE CROSS-POINT CELL ACTIVATION (SCPA) ARCHITECTURE FORULTRA-LOW-POWER SRAMS

This paper describes a single-bit-line cross-point cell activation (SC PA) architecture, which has been developed to reduce active power cons umption and to avoid increase in the size of high-density SRAM chips, such as 16-Mb SRAM's and beyond. A new PMOS precharging boost circuit, introduced to realize the single-bit-line structure, is also discusse d. This circuit is suitable for operation under low-voltage power supp ly conditions. The SCPA architecture with the new word-line boost circ uit is demonstrated with the experimental device, which is fabricated by 0.4-mu m CMOS wafer process technology.