A 16-MB CMOS SRAM WITH A 2.3-MU-M(2) SINGLE-BIT-LINE MEMORY CELL

A novel architecture that enables fast write/read in poly-PMOS load or high-resistance polyload single-bit-line cells is developed. The arch itecture for write uses alternate twin word activation (ATWA) with bit -line pulsing. A dummy cell is used to obtain a reference voltage for reading. An excellent balance between a normal cell signal line and a dummy cell signal link is attained using balanced common data-line arc hitecture. A newly developed self-bias-control (SBC) sense amplifier p rovides excellent stability and fast sensing performance for input vol tages close to V-CC at a low power supply of 2.5 V. The single-bit-lin e architecture is incorporated in a 16-Mb SRAM, which was fabricated u sing 0.25-mu m CMOS technology. The proposed single-bit-line architect ure reduces the cell area to 2.3 mu m(2), which is two-thirds of a con ventional two-bit-line cell with the same processes. The 16-Mb SRAM, a test chip for a 64-Mb SRAM, shows a 15-ns address access time and a 2 0-ns cycle time.