AN EXACT SOLUTION TO THE TRANSISTOR SIZING PROBLEM FOR CMOS CIRCUITS USING CONVEX-OPTIMIZATION

A general sequential circuit consists of a number of combinational sta ges that lie between latches. For the circuit to meet a given clocking specification. it is necessary for combinational stage to satisfy a c ertain delay requirement. Roughly speaking, increasing the sizes of so me transistors in a stage reduces the delay, with the penalty of incre ased area. The problem of transistor sizing is to minimize the area of a combinational stage, subject to its delay being less than a given s pecification. Although this problem has been recognized is a convex pr ogramming problem, most existing approaches do not take full advantage of this fact, and often give nonoptimal results. An efficient convex optimization algorithm has been used here. This algorithm is guarantee d to find the exact solution to the convex programming problem. We hav e also improved upon existing methods for computing the circuit delay as an Elmore time constant, to achieve higher accuracy. CMOS circuit e xamples, including a combinational circuit with 832 transistors are pr esented to demonstrate the efficacy of the new algorithm.