HARP - AN OPEN-ARCHITECTURE FOR PARALLEL MATRIX AND SIGNAL-PROCESSING

This paper describes and analyzes the Hybrid Array Ring Processor (HAR P) architecture. The HARP is an application specific architecture buil t around a host processor, shared memory, and a set of memory mapped p rocessing cells that are connected both into an open backplane and a b idirectional systolic ring. The architecture is analyzed through detai led simulation of a system implementation based on the Texas Instrumen ts TMS34082 floating point RISC. A bus controller is designed that pro vides a tightly coupled DMA function that accelerates systolic communi cation and supports new interleaved transparent communications and red uced overhead message passing. The architecture is benchmarked with th e matrix multiplication, FFT, QRD, and SVD algorithms.