YIELD ANALYSIS OF RECONFIGURABLE ARRAY PROCESSORS BASED ON MULTIPLE-LEVEL REDUNDANCY

We present and analyze a new multiple-level redundancy scheme based on hierarchical and element level redundancy for the enhancement of yiel d and reliability of large area array processors. This scheme can effe ctively tolerate not only the random defects/faults, but also the clus tered defects/faults. The analysis presented here is general in that i t takes into account the chip-kill defects occurring in the support ci rcuit area of the array processors and is applicable to a variety of a rray processors. We derive bounds for the support circuit area which w ill be useful in selecting the most cost-effective redundancy scheme f or a given application. The concept of subprocessing element-level red undancy is discussed and it is shown that a combination of subprocessi ng element-level redundancy with hierarchical redundancy offers signif icant yield improvements, especially for array processors with large a rea processing elements. The problem of optimal redundancy is also add ressed.