ADVANCED MULTILAYER METALLIZATION SCHEMES WITH COPPER AS INTERCONNECTION METAL

Advanced metallization schemes are needed to take advantage of the min iaturization of microelectronic devices which are performing at increa singly high speeds. The demands on metallization center around (af the increased resistance with lower cross-sectional areas and longer inte rconnect lengths and (b) stability with the surroundings during proces sing and use under high current densities and thin him stresses. A thr eefold attack is being pursued to solve these problems, which also dup licate the issues in packaging of these fast chips with large numbers of inputs and outputs: first is to make use of copper as the interconn ection metal; second is to use a multilevel metallization scheme; fina lly there is a need for a low dielectric constant dielectric. In this paper we present a review of progress made in addressing the first two schemes together with a brief discussion of the third. Copper, a here tofore undesired metal in silicon integrated circuits, seems to show p romise, with appropriate processing constraints, of fulfilling the pro jected needs of ultra-large-scale and giga-scale integration and perha ps even of packaging.