Pj. Wright et Yca. Shih, CAPACITANCE OF TOP LEADS METAL - COMPARISON BETWEEN FORMULA, SIMULATION, AND EXPERIMENT, IEEE transactions on computer-aided design of integrated circuits and systems, 12(12), 1993, pp. 1897-1902
The parasitic interconnection capacitance can significantly degrade th
e performance of an IC, In this paper, the parasitic capacitance of th
e top leads with a protective overcoat (PO) dielectric is modeled. For
a nitride only PO, the nitride increases the line-to-line capacitance
component by the average of the nitride and underlying oxide dielectr
ic constants with a maximum error of 11% according to two-dimensional
numerical simulations. If the oxide thickness of the PO is greater tha
n 0.2 mu m, then the line-to-ground component of capacitance will be w
ithin 10% of the value of a lead surrounded by oxide. The line-to-line
component of capacitance can have an error of over 30% and a modifica
tion is required to reduce the error. Two modifications for the nitrid
e/oxide PO are given; both increase the line-to-line capacitance by th
e fraction of nitride between the leads. The results of the modificati
ons and simulation are compared to experiment. The two-dimensional sim
ulations and formulas have a good fit to the experimental data.