A DELAY-BASED MODEL FOR CIRCUIT PARALLELISM

A new formal model for variable-delay simulators is presented for comp aring the effects of time base on circuit parallelism. This model more accurately reflects current simulation strategies than previous model s. Using this new model we show that parallelism is not a nondecreasin g function of time base. We bound parallelism, however, by two functio ns that converge to the unit-delay parallelism as the time base increa ses, preserving the intuition that coarser timing models result in gre ater parallelism. In addition, we corroborate the model predictions vi a an empirical study and discuss the impact of the results on synchron ous and conservative asynchronous parallel simulations.