PHYSICAL AND ELECTRICAL CHARACTERIZATION OF POLY BUFFERED LOCOS ISOLATION PROCESS FOR SUB 0.5-MU-M ULSI TECHNOLOGY

The scaling of mos devices has placed severe restrictions on the exten t of physical and electrical encroachment that can be generated by the isolation processes. The 0.4 mum generation of semiconductor memories typically requires an active area pitch of 0.8 mum with the correspon ding encroachment levels being less than 0.12 mum. In this study, the poly buffered LOCOS (PBL) isolation process has been evaluated to dete rmine its ability to satisfy the design as well as the manufacturing r equirements for this generation. For the first time, we demonstrate th at the PBL isolation process is capable of satisfying the requirements for 64 Mb DRAM/16 Mb SRAM generations.