SETTLING TIME REDUCTION TECHNIQUE FOR HIGH-SPEED DACS

Authors
KIM O KIM G KIM W
Citation
O. Kim et al., SETTLING TIME REDUCTION TECHNIQUE FOR HIGH-SPEED DACS, Electronics Letters, 29(25), 1993, pp. 2191-2192
Citations number
3
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
29
Issue
25
Year of publication
1993
Pages
2191 - 2192
Database
ISI
SICI code
0013-5194(1993)29:25<2191:STRTFH>2.0.ZU;2-5
Abstract
The ringing mechanism of the high impedance output node was analysed. To reduce this ringing, a new compensation circuit was developed and i mplemented in a standard CMOS process. This circuit can be programmed to cover a range of parameters. It is effective in minimising the sett ling time of a DAC.