AN OPTIMIZATION TECHNIQUE FOR THE DESIGN OF MULTIPLE-VALUED PLAS

Authors
ASARI KV ESWARAN C
Citation
Kv. Asari et C. Eswaran, AN OPTIMIZATION TECHNIQUE FOR THE DESIGN OF MULTIPLE-VALUED PLAS, I.E.E.E. transactions on computers, 43(1), 1994, pp. 118-122
Citations number
14
Categorie Soggetti
Computer Sciences","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
Journal title
I.E.E.E. transactions on computers → ACNP
ISSN journal
00189340
Volume
43
Issue
1
Year of publication
1994
Pages
118 - 122
Database
ISI
SICI code
0018-9340(1994)43:1<118:AOTFTD>2.0.ZU;2-U
Abstract
Am optimization technique for the design of two types of multiple-valu ed PLA's is described in this correspondence. In type-I PLA, the multi ple-valued function is realized directly, whereas in type-II PLA, outp ut encoding is used to encode the binary output of the PLA. In both ty pes, multiple function literal circuits are used for the purpose of mi nimization. It is shown that the proposed technique leads to a conside rably reduced size of PIA when compared to the earlier techniques.