EFFICIENT DIGITAL FILTERING ARCHITECTURES USING PIPELINING INTERLEAVING/

Citation
Zn. Jiang et An. Willson, EFFICIENT DIGITAL FILTERING ARCHITECTURES USING PIPELINING INTERLEAVING/, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 44(2), 1997, pp. 110-119
Citations number
22
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
10577130
Volume
44
Issue
2
Year of publication
1997
Pages
110 - 119
Database
ISI
SICI code
1057-7130(1997)44:2<110:EDFAUP>2.0.ZU;2-K
Abstract
A pipelining/interleaving (PI) technique is developed for efficient di gital filtering, By using a clock rate that is K times the data rate a nd with interleaved feedback of the output samples, a single expanded digital filter H(z(K)) can be made equivalent to a cascade of k identi cal filters H-k(z). 1 less than or equal to k less than or equal to K. The PI technique is used for designing Kaiser-Hamming sharpened linea r-phase FIR filters with very high performance, It can also be applied in efficient IIR filtering to alleviate the critical-loop limitation on system clock rates, Furthermore, the PI technique is applicable to designing efficient multirate signal processing systems.