This note describes the design of a programmable digital delay. An ana
logue signal (0-30 kHz) is digitized by a sample-and-hold plus 14-bit
analogue-to-digital converter and the resulting digital data is stored
in digital random access memory whose address is supplied by the para
llel output of programmable binary down counters. The stored digital s
amples are reconstructed (after a programmable delay) in analogue form
by a digital-to-analogue converter, so that the reconstructed signal
is a time-delayed version of the original analogue input signal. The a
mount of memory used, as well as the sampling rate, determines the max
imum possible delay.