LATENT DAMAGE AND PARAMETRIC DRIFT IN ELECTROSTATICALLY DAMAGED MOS-TRANSISTORS

The relationship between parametric drift and latent damage in ESD gat e-stressed MOSFETs is studied. Sub-breakdown damage causes minor chara cteristic distortion, which may remain undetected until failure. Howev er, such damage is only significant within a narrow stress-voltage win dow. Oxide breakdown may cause straightforward malfunction (i.e. catas trophic failure) or degraded transistor action. Degraded devices can d egenerate further under working voltages (0-10 V), providing a latent failure mechanism. Degradation phenomena are attributed to the intrusi on of polysilicon gate-material into the oxide and channel regions. Ca tastrophically failed and degraded devices are modelled using the PSpi ce circuit simulation system. The effects of degradation upon CMOS log ic operation are also examined.