A SIMPLIFIED SYNTHESIS OF TRANSMISSION-LINES WITH A TREE STRUCTURE

The limiting factor for high-performance systems is being set by inter connection delay rather than transistor switching speed. The advances in circuits speed and density are placing increasing demands on the pe rformance of interconnections, for example chip-to-chip interconnectio n on multichip modules. To address this extremely important and timely research area, we analyze in this paper the circuit property of a gen eric distributed RLC tree which models interconnections in high-speed IC chips. The presented result can be used to calculate the waveform a nd delay in an RLC tree. The result on the RLC tree is then extended t o the case of a tree consisting of transmission lines. Based on an ana lytical approach a two-pole circuit approximation is presented to prov ide a closed form solution. The approximation reveals the relationship between circuit performance and the design parameters which is essent ial to IC layout designs. A simplified formula is derived to evaluate the performance of VLSI layout.