AN ANALOG TEST TECHNIQUE FOR MASSIVELY-PARALLEL INTEGRATED-CIRCUITS AND SYSTEMS - AN APPROACH TO NEURAL NETWORKS CIRCUITS TESTING

The increase in integration density and in complexity of moderns integ rated circuits and systems revealed the necessity to consider the test ability problem at the design level of circuits. One of the most activ e research areas in circuits design, over the past decade, has been th e implementation of neural networks as electronic VLSI chips Especiall y, the implementation of artificial neural networks (ANN) as CMOs inte grated circuits shows several attractive features. Recent studies poin t out that classification is their most successful application field, and thus large networks will be required. Unfortunately, very few pape rs analyse the testability of electronic implementation of artificial neural networks. A large number of artificial neural networks models d eal with binary output neurones. This paper presents and discuss a glo bal current measurement based pseudo-analogue technique for digital-ou tput electronic neural networks testing. Two approaches have been pres ented and their limitations have been discussed. Simulation results an d a method validation test circuit have been presented.