SPADES-ACE - A SIMULATOR FOR PATH DELAY FAULTS IN SEQUENTIAL-CIRCUITSWITH EXTENSIONS TO ARBITRARY CLOCKING SCHEMES

Testing of synchronous sequential circuits for path delay faults requi res two sequences: a test sequence, that specifies the input values, a nd a clocking scheme, that specifies at what time units a fast clock s hould be applied. In this work, a fault simulator for path delay fault s in synchronous sequential circuits is described, that has the follow ing novel features. (1) For a given test sequence, all clocking scheme s that have a single fast clock are simulated in parallel. (2) During the simulation process, it is possible to determine a minimal set of c locking schemes to achieve the same fault coverage as in (1). (3) Alte rnatively, it is possible to simulate the test sequence under a given clocking scheme, containing multiple fast clacks at arbitrary time uni ts. (4) A path representation scheme is used, that allows efficient ac cess to path delay faults detected by previous tests. Experimental res ults are presented to demonstrate these features and their effectivene ss.