A LOW PARASITIC CAPACITANCE SCHEME BY THERMALLY STABLE TITANIUM SILICIDE TECHNOLOGY FOR HIGH-SPEED COMPLEMENTARY-METAL-OXIDE-SEMICONDUCTOR

This paper presents a dopant drive-out process from elevated source/dr ain (S/D) structures with titanium silicide local interconnects, which reduces not only the S/D areas but also junction capacitance in advan ced complementary-metal-oxide-semiconductor (CMOS) fabrication. A low- oxygen-content process with an optimized boron (B) doping realizes a t hermally stable titanium silicide with reduced Ti-B compound formation . Electrical measurements of the metal-oxide-semiconductor field effec t transistors (MOSFETs) show good I-V characteristics and high enduran ce to short-channel effects. Furthermore, the MOSFETs have hot-carrier and bias-temperature aging properties similar to those of controlled devices. Consequently, it has been clarified that the delay time per s tage of the MOSFETs with the local interconnects can be reduced with d ecreasing junction capacitance.