AN ADVANCED NAND-STRUCTURE CELL TECHNOLOGY FOR RELIABLE 3.3-V-64 MB ELECTRICALLY ERASABLE AND PROGRAMMABLE READ ONLY MEMORIES (EEPROMS)

An extremely small NAND-structure cell of 1.13 mu m(2) per bit, 80% of the smallest Flash memory cell reported so far [H. Kume et al.: IEEE Tech. Dig. IEDM (1992) p. 991], has been developed in 0.4 mu m technol ogy. The chip size of a 64 Mb NAND electrically erasable and programma ble read only memory (EEPROM) using this cell is estimated to be 120 m m(2), which is 60% that of a 84 Mb DRAM. In order to realize the small cell size, a 0.8 mu m field isolation is used. A negative bias of -0. 5 V to the P-well of the memory cell is applied during writing. In add ition, a bit-by-bit intelligent writing technology allows a 3.3 V data sensing scheme which can suppress read disturb to 1/1000 in compariso n with the conventional 5 V scheme. As a result, it is expected that w ith this technology, 10(6) write and erase cycles can be achieved and that the tunnel oxide can be scaled down from 10 nm to 8 nm.