BIPOLAR-TRANSISTOR WITH A BURIED LAYER FORMED BY HIGH-ENERGY ION-IMPLANTATION FOR SUBHALF-MICRON BIPOLAR-COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LSIS

We investigated a bipolar transistor with a buried layer formed by hig h-energy ion implantation without the epitaxitial silicon layer growth . We focused mainly on the reduction of junction leakage current relat ed to implantation damages, which could be achieved by rapid thermal a nnealing. Consequently, the maximum current gain of 155 and the cutoff frequency of 17.3 GHz were achieved with BVCEO=5.0 V. Moreover, this fabrication process is applicable to the conventional complementary me tal oxide semiconductor (CMOS) process with the retrograde twin wells without additional process steps. Therefore, this technique can be ver y promising for the fabrication of subhalf-micron BiCMOS LSIs.