A STUDY ON BILATERAL LATCH-UP SELF-TRIGGERING IN COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR PROTECTION CIRCUITS

The results of serial studies on the behavior of bilateral latch-up in complementary metal-oxide-semiconductor field effect transistor (CMOS ) protection circuits are presented. Bilateral latch-up self-triggerin g resulting from serial resistance or serial inductance on V-dd or V-s s is discussed. Optimizing the layout and design of output buffers to improve product performance and reliability is also recommended. The s tudies on the behavior of bilateral latch-up in CMOS protection circui ts are increasingly important since low-power applications are the fut ure trend.