EFFECTS OF DEVICE SCALING AND GEOMETRY ON MOS RADIATION HARDNESS ASSURANCE

In this work we investigate the effects of transistor scaling and geom etry on radiation hardness. The total-dose response is shown to depend strongly on transistor channel length. Specifically, transistors with shorter gate lengths tend to show more negative threshold-voltage shi fts during irradiation than transistors with longer gate lengths, Simi larly, transistors with longer gate lengths tend to show more positive threshold-voltage shifts during postirradiation annealing than transi stors with shorter gate lengths. These differences in radiation respon se, caused by differences in transistor size and geometry, will be imp ortant to factor into test-structure-to-IC correlations necessary to s upport cost-effective Qualified Manufacturers List (QML) hardness assu rance. Transistors with minimum gate length (more negative Delta V-th) will have a larger effect on ''standby'' power supply current for an IC at high dose rates, such as in a weapon environment, where worst-ca se response is associated with negative threshold-voltage shifts durin g irradiation. On the other hand, transistors with maximum gate length (more positive Delta V-th) Will have a larger effect on the timing pa rameters of an IC at low dose rates, such as in a space environment, w here worst-case response is represented by positive threshold-voltage shifts after postirradiation anneal. The channel size and geometry eff ects we observe cannot be predicted from simple scaling models, but oc cur because of real differences in oxide-, interface-, and border-trap charge densities among devices of different sizes.