THE LATCHUP RISK OF CMOS-TECHNOLOGY IN SPACE

The use of CMOS technology in space needs a careful evaluation of the latchup risk. The radiation tolerance is studied here for a standard 1 .0 mu m high density technology and its hardened variants. The interna l currents and densities are read through dynamic two/three dimensiona l device simulations, performed on a complete description of the CMOS inverter cell and a simulated heavy ion strike. An evaluation of the c apture cross section versus the ion energy is derived from the statist istical distribution of ion tracks through the structure.