A 10-B 20-MHZ 30-MW PIPELINED INTERPOLATING CMOS ADC

This paper describes a circuit design and experimental results of a vi deo-rate 10-b analog-to-digital converter (ADC) suitable for portable audio-visual equipment. Two new circuit techniques, termed pipelined c apacitive interpolation and error averaging circuits with capacitor ne tworks, are developed. As a result, very low power dissipation of 30 m W at a low power-supply voltage of 2.5 V is attained at the conversion frequency of 20 MHz. Also, a good DNL of less than +/- 0.5 LSB and an acceptable signal-to-noise and distortion ratio of 55 dB are obtained for the input frequencies of 1 kHz and 1 MHz, respectively. The ADC i s fabricated in 0.8-mum CMOS technology and occupies an area of 2.6 x 2.5 mm2.