A MONOLITHIC 2.3-GB S 100-MW CLOCK AND DATA RECOVERY CIRCUIT IN SILICON BIPOLAR TECHNOLOGY/

A monolithic clock and data recovery PLL circuit is implemented in a d igital silicon bipolar technology without modification. The only exter nal component used is the loop filter capacitor. A self-aligned data r ecovery architecture combined with a novel phase-detector design elimi nates the need for non-linear processing and phase shifter stages. Thi s enables a simpler design with low power and reduced dependence on th e bit rate. At 2.3 Gb/s, the test chip consumes 100 mW from a supply, excluding the input and output buffers. The worst-case rms jitter of t he recovered clock is less than 14 ps with 2(23) - 1 pseudorandom bit sequence.