VLSI CHIP SET FOR 2D HDTV SUBBAND FILTERING WITH ON-CHIP LINE MEMORIES

A chip set for 2D subband filtering of HDTV signals has been designed, fabricated and successfully tested. The two chips perform 10 14 qua drature mirror filtering for analysis filtering at the coder and synth esis filtering at the decoder. In order to achieve a very compact real ization, the architectures utilize all a priori known properties of th e filter algorithm. A 2D polyphase filter structure reduces the proces sing clock rate from the 72-MHz sampling rate to a moderate 18 MHz. Th e memory for vertical filtering is realized by on-chip parallel shift registers with multiphase clocking. A small silicon area for the filte r arithmetic is achieved by application of carry save adder trees with fixed filter coefficients represented by canonical signed digits. A c omplete filterbank for luminance and chrominance signals consists of f our identical chips, each with 450000 transistors on 92 mm2.