PARALLEL AND VECTOR LOGIC AND FAULT SIMULATION ALGORITHMS ON THE CRAYY-MP SUPERCOMPUTER

In this paper, we present parallel algorithms for logic and fault simu lation, developed for and implemented on the Cray Y-MP supercomputer, a general purpose shared-memory parallel machine with vector processor s. The parallel-and-vector version of the event-driven logic simulatio n algorithm achieves a speedup of 52 on the Cray Y-MP with 8 processor s, with a maximum performance of about 2 million events per second. Th ese results are comparable to the performance of hardware simulation e ngines and can be implemented on other parallel machines without major modifications. The second algorithm is a parallel and vector version of the parallel fault simulation algorithm. Experimental results on be nchmark circuits [1] show that very high evaluation rates (20 to 32x10 (9) evaluations/s.) can be achieved. Speedup factors of 45 to 69 are o bserved between the scalar and the parallel and vector execution of th e fault simulator.