FABRICATION OF SOI WAFERS WITH BURIED CAVITIES USING SILICON FUSION BONDING AND ELECTROCHEMICAL ETCHBACK

This paper describes a new technique for batch fabrication of silicon- on-insulator (SOI) wafers for microelectromechanical systems (MEMS) ap plications by silicon wafer bonding techniques. The process permits th e inclusion of buried cavities in the SOI wafers, providing a useful t ool for sensor and actuator fabrication using the resulting wafers. A low-cost electrochemical etchback step is used to define accurately th e thickness of the remaining single-crystal material even though the t wo wafers are bonded with an intermediate insulating oxide layer. The results presented include guidelines for backside contact definition w hich maximize the useful silicon area as a function of doping level. T he final single-crystal silicon thickness is uniform to within 0.05 mu m (standard deviation) and does not require any costly high-accuracy polishing steps.