FINITE BUFFER ANALYSIS OF MULTISTAGE INTERCONNECTION NETWORKS

We propose an analysis technique for a class of Multistage Interconnec tion Networks (MIN's) that have finite buffers at their switch inputs and operate in a synchronous packet-switched mode. We examine the issu e of clock period in design and analysis of synchronous MIN's and prop ose a model based on small clock periods. Then we analyze our ''small cycle'' design and compare the results with those obtained from the st andard ''big cycle'' model that is currently used. The significant per formance improvement of our model is shown based on various clock widt h, data width, and buffer length.