ANALOG FAULT SIMULATION IN STANDARD VHDL

Test development for analogue and mixed-signal circuits has become a b ottleneck in the IC development trajectory. A defect-oriented test app roach provides an objective test evaluation technique, which alleviate s this bottleneck. This test approach, however, makes extensive use of analogue fault simulation, which is very CPU-intensive. It is shown h ow a standard (digital) VI-IDL simulation environment can be used to d rastically reduce the fault simulation time for complex analogue circu its.