INDIUM-PHOSPHIDE MISIFET PROCESSING USING WET CHEMICAL SURFACE PRETREATMENTS AND EVAPORATED THIN SILICON INTERLAYERS

The use of thin silicon films with wet chemical surface pretreatment f or indium phosphide-insulator interface stabilisation of MiSiFETs is i nvestigated. InP MISiFETs prepared with the silicon interlayers deposi ted after H3PO4 surface pre-treatment show a decrease in hysteresis, f lat band voltage shift, and interface state density. Samples similarly prepared but using an HF surface pre-treatment show a higher threshol d voltage shift attributable to high fixed and interface charge densit y. These effects are consistent with existing models describing the in teraction of the silicon with the native oxide of indium phosphide.