LOGIC SYNTHESIS WITH HIGH-SPEED CMOS CIRCUIT TECHNIQUES

Systems for automated logic synthesis with the True Single Phase Clock ing circuit technique (TSPC) and a modified form of the Clock and Data Precharged Dynamic (CDPD) circuit technique, are presented. The CDPD system synthesizes high speed one clock cycle modules of unate Boolean functions in short design time. A novel true single phase clocking (T SPC) flip-flop suitable for CDPD synthesis simplifies interfacing with standard edge triggered clocking schemes. Also, a TSPC cell library f or automatic logic synthesis with the TSPC circuit technique is presen ted. The library is targeted for high performance DSP applications. Fa bricated test circuits synthesized by both the CDPD and TSPC synthesis systems in a 0.8 mu m standard CMOS process are described and their p erformance is verified. Clock frequencies up to 700MHz were measured.