We show that the reverse short channel effect (RSCE) is reduced in NMO
S devices made in thick silicon-on-insulator (SOI) material. The reduc
tion of the RSCE depends on the thickness of the Si overlayer. It is f
ound that the thinner the Si film, the less the threshold voltage roll
-on. The experimental findings are explained by a decrease of the late
ral distribution of silicon interstitials generated at the source and
drain (S/D) region and are related with their high recombination veloc
ity at the buried oxide. This method can be used to separately test th
e influence of S/D point defects on the RSCE from other different hypo
theses reported in the literature. Coupled process-device simulation r
eveals that the method is very sensitive to fundamental point defect p
roperties.