SILICON NPN BIPOLAR-TRANSISTORS WITH INDIUM-IMPLANTED BASE REGIONS

In this paper, silicon npn bipolar transistors with indium-implanted b ase regions are discussed, Polysilicon emitter bipolar transistors lir e fabricated using a standard 0.5-mu m BIC-MOS process flow [1] where the base BF2 implant is replaced by an indium implant, In indium-impla nted transistors, the integrated hole concentration (G(b)) in the quas i-neutral base is reduced due to incomplete ionization of indium accep tor states, The novel utilization of this impurity freeze-out effect r esults in much increased collector currents and common-emitter transis tor gains (h(fe)) compared to boron-implanted transistors, Also, since indium acceptor states in depletion regions become fully ionized, the spreading of the reverse-biased collector-base junction depletion reg ion into the transistor base (base-width modulation) is minimized, Hen ce, for indium base bipolar transistor an improved h(fe)-V-A product i s anticipated, Our first attempt at fabricating bipolar transistors wi th indium-implanted base regions resulted in devices with greatly incr eased collector current, impressive gains of h(fe) approximate to 1600 , excellent collector current saturation characteristics, an Early Vol tage of V-A approximate to 10 V, h(fe)-V-A product of 16000 (implying an extended device design space), base-emitter breakdown voltages of B VEBO approximate to 9.6 V, and a cut-off frequency of f(t) = 17.8 GHz.