SPECIAL-PURPOSE HARDWARE FOR DISCRETE FOURIER-TRANSFORM IMPLEMENTATION

Authors
CONNER M TOLIMIERI R
Citation
M. Conner et R. Tolimieri, SPECIAL-PURPOSE HARDWARE FOR DISCRETE FOURIER-TRANSFORM IMPLEMENTATION, Parallel computing, 20(2), 1994, pp. 215-232
Citations number
12
Categorie Soggetti
Computer Sciences","Computer Science Theory & Methods
Journal title
Parallel computing → ACNP
ISSN journal
01678191
Volume
20
Issue
2
Year of publication
1994
Pages
215 - 232
Database
ISI
SICI code
0167-8191(1994)20:2<215:SHFDFI>2.0.ZU;2-9
Abstract
Parallel hardware implementation of a 'pre-addition' matrix for the fi rst step of a Fourier transform on n points where n is the product of either two or three discrete primes is described. A set of adders with a small amount of temporary memory is required; input and output is b y a common bus. The individual microprograms for each processor are de scribed. Detailed pipeline timings are given showing a nearly perfect hardware utilization. The examples of 35 and 105 point transforms are followed in detail.