A NEW DYNAMIC TEST VECTOR COMPACTION FOR AUTOMATIC TEST PATTERN GENERATION

Authors
AYARI B KAMINSKA B
Citation
B. Ayari et B. Kaminska, A NEW DYNAMIC TEST VECTOR COMPACTION FOR AUTOMATIC TEST PATTERN GENERATION, IEEE transactions on computer-aided design of integrated circuits and systems, 13(3), 1994, pp. 353-358
Citations number
19
Categorie Soggetti
Computer Application, Chemistry & Engineering","Computer Science Hardware & Architecture
Journal title
IEEE transactions on computer-aided design of integrated circuits and systems → ACNP
ISSN journal
02780070
Volume
13
Issue
3
Year of publication
1994
Pages
353 - 358
Database
ISI
SICI code
0278-0070(1994)13:3<353:ANDTVC>2.0.ZU;2-F
Abstract
In this paper, a new approach for dynamic test vector compaction, for combinational logic circuits, called COMPACT, is proposed. A new data structure of test vectors permits easy verification of compactability between test vectors with minimal memory requirements. Experimental re sults obtained by adding the proposed algorithm to a simple PODEM prog ram and applying it to the ISCAS-85 benchmark circuits are presented. The resulting test vector reduction is up to 40% for small circuits an d around 50% for the large circuits (over 1000 gates).