A STATE ASSIGNMENT APPROACH TO ASYNCHRONOUS CMOS CIRCUIT-DESIGN

We present a new algorithm for state assignment in asynchronous circui ts so that for each circuit state transition, only one (secondary) sta te variable switches. No intermediate unstable states are used. The re sultant circuits operate at optimum speed in terms of the number of tr ansitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching e vents is reduced and dynamic power dissipation may also be reduced. Ou r approach is suitable for asynchronous sequential circuits that are d esigned from flow tables or state transition diagrams. The proposed ap proach may also be useful for designing synchronous circuits, but expl orations into the subject of clock power would be necessary to determi ne its usefulness.