AREA-TIME OPTIMAL ADDER DESIGN - COMMENTS

A previous paper by Wei and Thompson defined a family of adders based on a modular design and presented an excellent systematic method of im plementing a VLSI parallel adder using three types of component cells designed in static CMOS. Their approach to the adder design was based on the optimization of a formulated dynamic programming problem with r espect to area and time. In this work, we first explicitly demonstrate the optimal 32-bit fast carry generator, described by Wei and Thompso n, is incorrect. With suitable corrections, a correct 32-bit fast carr y generator design is then presented. Next, BiCMOS technology is appli ed to implement the subcircuit of fast carry generator to accelerate t he critical path. We show that the critical path delay of 16-bit, 32-b it and 66-bit adders is respectively shortened to 83.89%, 86.89% and 9 0.62% after introducing the BiCMOS drivers.