HOT-CARRIER-RELIABILITY DESIGN GUIDELINES FOR CMOS LOGIC-CIRCUITS

Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulat or BERT can predict CMOS digital circuit speed degradation from transi stor dc stress data. We present generalized hot-carrier-reliability de sign rules that translate device-level degradation rate to CMOS circui t lifetime. The design rules, which consist of lifetime and speed degr adation factors, can roughly predict CMOS circuit degradation during t he initial design, and can help reliability engineers to quickly estim ate the overall product hot-carrier reliability. The NMOSFET and PMOSF ET lifetime factors were found to obey 4/ft(rise) and 10/ft(fill) resp ectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current a s the monitor, while for a 100 MHz operating frequency and for an inpu t rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 a nd 300, respectively.